The subject invention is directed generally to digital multiplier arrays, and more particularly to a digital multiplier array having an input for receiving an operand in carry-sum form.
In the text book DIGITAL COMPUTER ARITHMETIC Design and Implementation, Cavanaugh, McGraw-Hill, 1984, multiplication is defined as the repeated addition of the multiplicand, where the number of times it is added is defined by the multiplier. Each step generates a partial product and the result of the final addition is the product. This is analogous to what is done in long hand multiplication as a series of shift-add operations.
Digital multiplier architectures have generally been directed to avoiding the repeated addition procedure and the shift-add procedure, both of which are time consuming and inefficient. Known digital multiplier architectures have included array multipliers wherein the multiplicand and the multiplier are given by standard binary vectors, and the product is encoded in a carry and sum word pair. The encoded product representation can be converted into standard binary representations by arithmetically adding the carry and sum words, for example for use by another array multiplier.
A consideration with known array multipliers is the processing time required to convert multiplication products from carry and sum representation to binary representation.